Minterms, don't-cares, truth table, and simplified SOP.

Simplify minterm-based Boolean functions.

Check setup slack and estimated Fmax.

Calculate setup and hold slack from timing values.

Binary, decimal, hex, octal, signed, and unsigned views.

Boolean laws, K-map rules, setup/hold formulas, and tips.

Signed decimal to fixed-width binary and hex.

State encodings, transition table, and Verilog skeleton.

Generate a clean module shell with ports, clock, and reset.

Estimate depth from burst, stall, and rate mismatch.

Divider value, actual frequency, error, and counter width.

Setup and hold slack with latency and uncertainty.

Truth tables and starter Verilog for common logic blocks.

Slack, skew, timing requirements, and violations.

States, transitions, Moore/Mealy, and RTL structure.

Occupancy, depth sizing, flags, and CDC basics.

Gray-code ordering, grouping, and simplified SOP.

Signed range, encoding, sign extension, and overflow.

Timing paths, corners, uncertainty, slack, and closure.

Components, transaction flow, checking, and coverage.