Timing fundamentals

Static timing analysis basics

STA checks every constrained timing path mathematically, without simulation vectors, to determine whether data can be captured reliably at the target clock frequency.

Level: FoundationRead: 7 minutesRelated: RTL and Physical Design

Timing path anatomy

Startpoint→Cell delay+Net delay→Endpoint

Common path types are register-to-register, input-to-register, register-to-output, and input-to-output.

Each path has an arrival time and a required time. Slack is the remaining timing margin after accounting for delays and constraints.

Setup and hold checks

Setup slack = latest required time - latest arrival time
Hold slack = earliest arrival time - earliest required time
Negative slack = violation

Setup is a maximum-delay check and is related to clock period. Hold is a minimum-delay check around the capture edge and is not repaired by simply lowering frequency.

Corners and uncertainty

Delay changes with process, voltage, and temperature. Analysis also includes clock latency, skew, jitter/uncertainty, derates, and timing exceptions. Setup often becomes harder at slow data conditions; hold often becomes harder at fast data conditions, but the actual signoff setup depends on the library and methodology.

Simple setup check

Required time = 4.70 ns and arrival time = 4.95 ns. Slack = 4.70 - 4.95 = -0.25 ns, so the path fails setup by 250 ps.

Possible fixes include reducing data-path delay, improving placement/routing, adjusting the pipeline, or reviewing valid constraints.

Common mistakes

  • Looking only at total negative slack while ignoring the worst path and path groups.
  • Fixing a timing report before checking whether clocks and I/O delays are constrained correctly.
  • Applying false-path or multicycle exceptions without proving functional intent.
  • Assuming setup fixes cannot create hold problems, or vice versa.
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