RTL fundamentals

Finite state machines

An FSM stores the current operating state and selects the next state from inputs. It is a clean way to implement protocols, controllers, and sequences.

Level: FoundationRead: 6 minutesRelated: RTL Design

State, transition, output

IDLE→ start →LOAD→ valid →RUN→ done →IDLE

Every transition should have a defined condition, including the behavior when no condition is true.

A synchronous FSM normally has a state register, next-state combinational logic, and output logic.

Moore and Mealy

  • Moore: outputs depend only on current state. Outputs are usually easier to reason about and remain stable between state changes.
  • Mealy: outputs depend on current state and inputs. It can respond within the current cycle but needs careful glitch and timing analysis.
Moore: output = f(current_state)
Mealy: output = f(current_state, inputs)
Next state = f(current_state, inputs)

Worked example

Three-state transfer controller

IDLE waits for start. LOAD waits for valid data. RUN asserts busy until finish, then returns to IDLE.

With three states, binary encoding needs ceil(log2(3)) = 2 state bits. One-hot encoding uses 3 bits but can simplify decode logic.

Common mistakes

  • Leaving next-state or outputs unassigned, which infers latches.
  • Not defining a reset state or recovery from an illegal state.
  • Mixing sequential state updates and combinational transition logic carelessly.
  • Using Mealy outputs without considering input glitches.
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