Transaction flow
Sequence→Sequencer→Driver→DUT→Monitor→Scoreboard
Stimulus flows toward the DUT. Observed transactions flow independently from monitors to checking and coverage.
Core components
- Sequence item: a transaction such as a bus read or packet.
- Sequence and sequencer: create and arbitrate transaction streams.
- Driver: converts transactions into pin-level DUT activity.
- Monitor: observes interface activity without driving it.
- Scoreboard: compares actual behavior with expected behavior.
- Agent, environment, test: organize reusable components and scenario configuration.
Example verification flow
Verify a synchronous FIFO
A sequence creates randomized write and read transactions. The driver applies valid handshakes. A monitor reconstructs accepted transfers. A reference model tracks expected queue contents, and the scoreboard compares every observed read.
Functional coverage records empty/full boundaries, simultaneous read/write, wraparound, and important depth transitions.
Phases and objections
Components are created and connected during build/connect phases. Time-consuming stimulus normally runs in run phase. A test raises an objection while activity is required and drops it when the scenario is complete.
Common mistakes
- Starting UVM before learning SystemVerilog classes, interfaces, randomization, and assertions.
- Putting protocol checking inside the driver instead of using independent monitors/checkers.
- Using a scoreboard without a clear reference model.
- Collecting coverage without connecting it to a verification plan.