Practice problems

Practice problems.

Choose a focused RTL problem, write the code, run checks, then compare with the solution.

MUX 2:1 MUX Write a basic combinational selector using a, b, and sel. Easy EDG Rising Edge Detector Generate a one-cycle pulse when an input rises from 0 to 1. Easy CNT 4-bit Counter with Enable Build a resettable counter that increments only when enable is high. Easy ENC 4-bit Priority Encoder Encode the highest-priority asserted request bit. Medium FSM Sequence Detector 1011 Design a Moore FSM that detects overlapping serial input sequences. Medium FIFO FIFO Full/Empty Logic Create pointer-based full and empty flags for a synchronous FIFO. Hard MUX 4:1 MUXSelect one of four inputs using a 2-bit select line. Easy STA Setup Slack CalculationCompute setup slack from period, delays, setup time, and skew. Easy DFT Scan Chain ConceptImplement a small scan shift register with scan enable. Easy CLK Clock DividerToggle an output clock after a fixed number of input cycles. Medium FSM Sequence Detector 1101Design an overlapping Moore FSM for another serial sequence. Medium FSM Traffic Light ControllerBuild a timed FSM for red, green, and yellow states. Medium STA Hold Violation DebugFind hold slack and decide whether the path violates timing. Medium CDC CDC 2-Flop SynchronizerSynchronize a single-bit signal into a destination clock domain. Medium UVM UVM Monitor SkeletonWrite the structure of a monitor that samples interface transfers. Medium SB Simple ScoreboardCompare expected and actual values and report mismatches. Medium SVA Valid-Ready AssertionWrite an assertion for valid-ready data stability. Medium BUF Valid-Ready Skid BufferHandle backpressure while preserving one transfer. Hard CDC Pulse SynchronizerMove a pulse safely between clock domains using toggle sync. Hard