Preparation Hub

Choose your VLSI domain and build preparation step by step.

Start with domain overviews, then move into practice tools, quiz reports, project direction, and resume readiness when you want deeper preparation feedback.

Explore Domains Take Basic Quiz

Explore Domains

Choose a domain to open its detailed preparation page.

RTL RTL Design

Hardware logic, Verilog, FSM, datapath, AMBA basics.

 DV Design Verification

SystemVerilog, UVM, assertions, coverage, debug.

 PD Physical Design

Floorplan, CTS, routing, STA, signoff basics.

 DFT DFT

Scan, ATPG, JTAG, MBIST, fault coverage.

 ANA Analog Layout

CMOS, DRC/LVS, matching, parasitics, layout mindset.

 EMB Embedded

C, MCU, UART, SPI, I2C, interrupts, timers.

Core topics

Build the concepts used across VLSI domains.

Each lesson includes an explanation, key equations, a worked example, common mistakes, and a related practice tool.

STASetup and Hold

Slack, skew, requirements, and timing violations.

 FSMFinite State Machines

States, transitions, Moore/Mealy, and RTL structure.

 FIFOFIFO Fundamentals

Occupancy, depth sizing, flags, and CDC basics.

 KMKarnaugh Maps

Gray-code ordering, grouping, and simplified SOP.

 2C2's Complement

Signed range, encoding, extension, and overflow.

 STASTA Basics

Paths, delay, uncertainty, corners, and closure.

 UVMUVM Basics

Testbench components, transactions, and checking.

Practice tools

Build fundamentals with quick digital design utilities.

Use compact calculators for K-maps, Boolean simplification, timing checks, number conversion, and design formulas.

KM K-Map Generator

Minterms, don't-cares, truth table, and simplified SOP.

 BS Boolean Simplifier

Simplify minterm-based Boolean functions.

 TP Timing Path Checker

Check setup slack and estimated Fmax.

 SH Setup/Hold Calculator

Calculate setup and hold slack from timing values.

 NS Number Converter

Binary, decimal, hex, octal, signed, and unsigned views.

 FS Formula Sheet

Boolean laws, K-map rules, setup/hold formulas, and tips.

 2C 2's Complement Calculator

Signed decimal to fixed-width binary and hex.

 FSM FSM Helper

State encodings, transition table, and Verilog skeleton.

 RTL Verilog Module Template

Generate a clean module shell with ports, clock, and reset.

 FIFO FIFO Depth Calculator

Estimate depth from burst, stall, and rate mismatch.

 CLK Clock Divider Calculator

Divider value, actual frequency, error, and counter width.

 STA STA Advanced Calculator

Setup and hold slack with latency and uncertainty.

 MD MUX / Decoder Generator

Truth tables and starter Verilog for common logic blocks.