Sequence Detector 1011

Design a Moore FSM that detects the serial bit sequence 1011. Overlapping sequences must be detected.

Medium FSM RTL Design Suggested: 30 minutes

Task

Create a Moore finite state machine with one serial input bit and one output. The output must go high for one clock cycle when the sequence 1011 is detected.

Requirements

Input bits arrive one per clock on din.
Reset is active-low and asynchronous.
Use a Moore output based on the current state.
Overlapping sequences must work. Example: input 1011011 should detect twice.

Your answer

Do not use AI.

This limited checker reads the expected FSM coding style and compares its state-transition model with example streams. It does not compile or simulate Verilog. Validate your complete design with a simulator and testbench.

module sequence_detector_1011 (
  input  wire clk,
  input  wire rst_n,
  input  wire din,
  output reg  detected
);

  // Write your FSM here

endmodule

Ready to check structure. Checks inspect a limited parsed state model. They do not compile or simulate Verilog.

Hint

Track how much of 1011 has already matched. Use states for no match, 1, 10, 101, and 1011 detected.

After matching 101, a new 1 completes the sequence.
For overlap, the detected state should keep the useful suffix. After detecting 1011, the last bit is also the start of a possible next sequence.
Keep next-state logic separate from the state register for cleaner RTL.

One possible solution

module sequence_detector_1011 (
  input  wire clk,
  input  wire rst_n,
  input  wire din,
  output reg  detected
);

  localparam S_IDLE = 3'd0;
  localparam S_1    = 3'd1;
  localparam S_10   = 3'd2;
  localparam S_101  = 3'd3;
  localparam S_1011 = 3'd4;

  reg [2:0] state;
  reg [2:0] next_state;

  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      state <= S_IDLE;
    else
      state <= next_state;
  end

  always @(*) begin
    case (state)
      S_IDLE: next_state = din ? S_1 : S_IDLE;
      S_1:    next_state = din ? S_1 : S_10;
      S_10:   next_state = din ? S_101 : S_IDLE;
      S_101:  next_state = din ? S_1011 : S_10;
      S_1011: next_state = din ? S_1 : S_10;
      default: next_state = S_IDLE;
    endcase
  end

  always @(*) begin
    detected = (state == S_1011);
  end

endmodule

Why this works

Each state stores the longest suffix of the received stream that is also a prefix of 1011. That is what allows overlap detection without restarting too aggressively.

Testbench idea

Drive a known bit stream and count the cycles where detected becomes high.

// Try streams such as:
// 1011      -> one detection
// 1011011   -> two overlapping detections
// 000101100 -> one detection

task send_bit(input bit value);
  begin
    din = value;
    @(posedge clk);
  end
endtask

Common mistakes

Forgetting overlap handling after the detected state.
Making detected depend directly on din in a Moore FSM.
Missing a default state in combinational next-state logic.